We have 20+ years of experience in delivering superior and innovative products



22, Sin Ming Lane, #05-75 Midview City Singapore 573969


(+65) 6777-2240 / 6570 6086

Join Our Team

We have ongoing opportunities for enthusiastic and motivated individuals who have the experience, skills, and drive to join our team and help propel us forward.

Please check the current job opportunities below that are open for application.

Please send your Resume to hr@advinno.com.

Job Openings

Job Description:

  1. Design and development of ASIC, FPGA, PCB and Embedded based systems.
  2. Expert level in Verilog/VHDL coding, System Verilogand UVM.
  3. Design verification and synthesis of ASIC/FPGA chips
  4. Experience in firmware or software application development with C or C++.
  5. Involve in System Architectural definition, hardware/software system integration, testing and troubleshooting.
  6. Participate in new products definition and design.
  7. Provide technical support to customers.

Job Requirements:

  1. Candidate should possess a bachelor’s or master’s degree in the field of Electrical or Electronics Engineering, Computer Science or equivalent.
  2. At least 3 years of experience in ASIC/FPGA/Embedded system design.
  3. In-depth knowledge and expertise in VHDL, Verilog, System-Verilog, UVM, C and C++.
  4. Well versed of ASIC/Xilinx/Altera design flow.
  5. Familiar with UNIX/Linux environment and scripting.
  6. Self-motivated, creative, resourceful, strong analytical and troubleshooting skills.
  7. Should be able to work independently, has a good team spirit, a strong sense of responsibility, a creative problem solver and be easy to get along with others.

Job Description:

  • Responsible for IP level and/or SOC level verification.
  • Develop verification plan for complex digital IP from design spec, work closely with design engineers to identify important verification scenarios.
  • Create verification environment/testbench with Bus Functional Model (BFM) using SystemVerilog, UVM and/or System C.
  • Identify and implement functional coverage and SystemVerilog Assertions to catch functional bugs and to boost design quality prior to tape-out.
  • Develop directed/use case/random test cases using SystemVerilog, analyse test results, debug tests and improve verification quality.
  • Knowing to use Formal verification with SystemVerilog Assertion (SVA) to verify IP block is a plus.


  • Bachelor/Master’s degree in Electrical & Electronics/Computer Engineering or equivalent.
  • Familiar with AMBA bus protocol (AXI, CHI, ACE, APB).
  • Experience with verification methodology such as SystemVerilog, OVM, UVM, SystemC.
  • Experience with functional coverage/SVA assertions and test sequence/case writing.
  • Experience with the full verification execution cycle.
  • Experience in developing measurable verification plan.
  • Experience with function verification for common SoC building blocks and verification IP for NOC/Interconnect/Fabric/PCIE, etc. are added advantages.
  • Strong problem solver, communicator and team player.
  • Scripting skills in Perl, Python, TCL, shell, etc.

Job Description:

  1. Work with IC Design engineer to design and layout custom RF, analog and mixed-signal circuits from sub-blocks to top-level integration and verification.
  2. Perform physical design verifications (LVS/DRC/ERC).
  3. Collaborate with IC Design engineers to optimize layout implementation for better power, performance, and area.
  4. Responsible for full-chip physical verification sign-off and tape out.
  5. Good understanding of semiconductor and circuit design.

Job Requirements:

  1. Bachelor degree in Electrical and Electronics Engineering or equivalent.
  2. At least three (5+) or more years of RF, analog /mixed custom layout design experience.
  3. Experience with schematic-driven layout, floor planning, chip level routing, design rule and physical verification and chip integration.
  4. Good understanding of critical device matching, high voltage layout techniques, advance node Pmos/ Nmos guarding.
  5. Good knowledge of design manual.
  6. Good Knowledge of CAD tools (Cadence Virtuoso, Mentor Calibre DRC/LVS/ERC, Synopsys Hercules, Cadence PVS ).
  7. Must have good analysis and trouble shooting skills.
  8. Should be able to work independently, self-motivated, has a good team spirit, a strong sense of responsibility and urgency, a creative problem solver and hardworking.
  9. Good communication skills in written and verbal English.