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Catapult High-Level Synthesis and Verification
Catapult High-Level Synthesis and Verification
Catapult has the broadest portfolio of hardware design solutions for C++ and SystemC-based High-Level Synthesis (HLS). Catapult’s physically-aware, multi-VT mode, with Low-Power estimation and optimization, plus a range of leading Verification solutions make Catapult HLS more than just "C to RTL".
The past several years have seen an explosion in the adoption of HLS for chip design driven by increasing design and verification complexity as well as time to market pressures. Catapult HLS enables designers to get their chips to market faster by shortening the overall design and verification flow.
Key Catapult HLS Solutions:
- C++/SystemC High-Level Synthesis
- ASIC and FPGA targeting
- Low-Power ASIC RTL generation
- AI/ML design acceleration
- Code and functional coverage
- Formal verification
- RTL equivalence checking (SLEC)
- High-level SystemC simulation
C++/SystemC Synthesis
A comprehensive HLS flow taking C++ or SystemC as the design input and optimally targeting ASIC, eFPGA or FPGA implementations tuned for frequency and target technology.
- C++ and SystemC language support
- FPGA and ASIC independence
- Frequency and technology-tuned RTL output
- eFPGA targeting support
Low-Power Solutions
When it comes to early design space exploration, power estimation, and optimizing for low-power ASIC RTL, Catapult generates highly efficient RTL that is optimized with our PowerPro technology under the hood.
- Early design space exploration for power
- ASIC power estimation and optimization
- PowerPro technology integration
- Physically-aware multi-VT mode optimization
AI Solutions
Catapult AI enhances HLS for accelerated design exploration, quantization analysis and performance, power and area prediction.
- Accelerated AI/ML design exploration
- Quantization analysis and performance tuning
- Power and area prediction
- Deep learning and computer vision support
Catapult High-Level Verification Solutions:
Accelerate your High-Level Verification (HLV) flow with known and trusted methods using the Catapult HLV Platform. Reduce your overall SoC verification turnaround time and costs by up to 80% leveraging High-Level Design Checking, Code/Functional Coverage, and static plus formal methods.
Catapult Coverage
HLS-aware code coverage including support for statement, branch, condition, expression (FEC) and array access coverage plus SystemVerilog-inspired functional coverage with support for covergroups, coverpoints, bins and crosses.
- Statement, branch, condition, and expression (FEC) coverage
- Array access coverage
- SystemVerilog-inspired functional coverage
- Covergroups, coverpoints, bins, and crosses
Catapult Formal Verification
Formally find mistakes, ambiguities and problem design issues or user constraint mistakes early in the HLS process. Even with differences in timing, and interfaces, Catapult Formal enables verification and a coverage closure flow.
- Early HLS mistake and ambiguity detection
- Handles timing and interface differences
- Coverage closure flow
- Static and formal verification methods
SLEC System
Check the correctness of RTL against your High-Level models using SLEC. Enabling proof that specification and implementation are identical despite differences in language, timing, or abstraction.
- RTL correctness verification against high-level models
- Language and abstraction-level independence
- Formal proof that specification and implementation are identical
Questa HL-SystemC
High-level design verification with Questa HL-SYC expansion helps eliminate issues before synthesis by starting verification earlier in the flow.
- Verification before synthesis
- Eliminate issues earlier in the design flow
- Reduce SoC verification turnaround time by up to 80%
