ASIC Design Services

Advinno offers “Specification to Chip” design services. The team comprised of experienced engineering professionals with areas of expertise across the entire design flow. Advinno has a proven track record in taking complex ASIC designs from design specification through tape-out. Our team can help you in any stages of the design flow from architectural exploration, logic design, physical implementation, verification to final chip.

Logic Design and Verification

Design Specification
RTL Design
Functional Verification
Static Timing Analysis (STA)
FPGA Prototyping
Design for Test (DFT)

Physical Implementation and Verification

Physical Design
Physical Verification
Timing Closure

Advinno has successfully implemented full-chip and block level customer tape-outs in sub-micron technology. Many SoC development projects have been completed in market segments including portable devices, consumer electronics, and wired and wireless networking. Advinno has and continues to implement first time success working silicon. Our team focuses on addressing the unique requirements of your design including ultra low power operation, stringent die size requirements, high speed interface design, complex analog and mixed signal IP integration.

We aim to exceed your expectations.