Analog Layout Services

  • Over the last 18+ years, Advinno has been involved in layouts on many analog and mixed-signal chips. Advinno has been involved in tape outs targeted to 14nm/10nm/7nm process nodes. Advinno team has experience with TSMC, UMC, Global, Intel Foundries. The team has expertise in SerDes, PMUs, RF designs, Memories, Data Converters, and IOs Design Specification
Expertise
 
  • Block level and full chip layouts
  • Floor planning, Placement, Routing
  • Matching transistor pairs
  • Shielding critical nets
  • EM&IR analysis and repair
  • DRC/LVS
  • Full chip integration
  • Expertise in ADC/DAC, PLL, DLL, LNA, IOs, Serdes, DC/DC Converters, Oscillators, Memories, PMUs and RF layouts
  • Foundries: Expertise in TSMC, UMC, Global Foundries, Tower Jazz, X-Fab, Micrel, Dongbu and Samsung
  • Process Nodes: 500nm all the way down to 16nm/14nm/10nm/7nm
  • Expertise in Bulk CMOS, SOI and BCD processes