{"id":6342,"date":"2024-01-15T11:02:07","date_gmt":"2024-01-15T04:02:07","guid":{"rendered":"https:\/\/www.advinno.com\/?page_id=6342"},"modified":"2026-04-16T13:33:58","modified_gmt":"2026-04-16T06:33:58","slug":"careers","status":"publish","type":"page","link":"https:\/\/www.advinno.com\/sg\/careers\/","title":{"rendered":"\u804c\u4e1a\u673a\u4f1a"},"content":{"rendered":"<div data-elementor-type=\"wp-page\" data-elementor-id=\"6342\" class=\"elementor elementor-6342\" data-elementor-post-type=\"page\">\n\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-69dd69a ot-traditional elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"69dd69a\" data-element_type=\"section\" data-e-type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-cf2cdfb ot-flex-column-vertical\" data-id=\"cf2cdfb\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-3fdd27a elementor-widget elementor-widget-heading\" data-id=\"3fdd27a\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Join Our Team<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-a12a1d2 elementor-widget elementor-widget-text-editor\" data-id=\"a12a1d2\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p><span style=\"font-size: 14pt;\">We have ongoing opportunities for enthusiastic and motivated individuals who have the experience, skills, and drive to join our team and help propel us forward.<\/span><\/p><p><span style=\"font-size: 14pt;\">Please check the current job opportunities below that are open for application.<\/span><\/p><p><span style=\"font-size: 14pt;\">Please send your Resume to <a href=\"mailto:hr@advinno.com\">hr@advinno.com<\/a>.<\/span><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-89d470e elementor-widget elementor-widget-heading\" data-id=\"89d470e\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h3 class=\"elementor-heading-title elementor-size-default\">Job Openings<\/h3>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-a129946 elementor-widget elementor-widget-accordion\" data-id=\"a129946\" data-element_type=\"widget\" data-e-type=\"widget\" data-settings=\"{&quot;_animation&quot;:&quot;none&quot;}\" data-widget_type=\"accordion.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-accordion\">\n\t\t\t\t\t\t\t<div class=\"elementor-accordion-item\">\n\t\t\t\t\t<div id=\"elementor-tab-title-1681\" class=\"elementor-tab-title\" data-tab=\"1\" role=\"button\" aria-controls=\"elementor-tab-content-1681\" aria-expanded=\"false\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon elementor-accordion-icon-left\" aria-hidden=\"true\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon-closed\"><i class=\"far fa-plus-square\"><\/i><\/span>\n\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon-opened\"><i class=\"far fa-minus-square\"><\/i><\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t<a class=\"elementor-accordion-title\" tabindex=\"0\">Senior AI\/ASIC\/FPGA\/Embedded Design Engineers<\/a>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<div id=\"elementor-tab-content-1681\" class=\"elementor-tab-content elementor-clearfix\" data-tab=\"1\" role=\"region\" aria-labelledby=\"elementor-tab-title-1681\"><p><strong>Job Description: <\/strong><\/p><ol><li>Design and development of ASIC, FPGA, PCB and Embedded based systems.<\/li><li>Expert level in Verilog\/VHDL\/System Verilog\/UVM<\/li><li>Experience in firmware or software application development with C or C++<\/li><li>Experience with ML, deep learning, PyTorch, TensorFlow, Python, NLP<\/li><li>Design verification and synthesis of AI\/ASIC\/FPGA chips<\/li><li>Involve in System Architectural definition, hardware\/software system integration, testing and troubleshooting<\/li><li>Participate in new products definition and design<\/li><li>Provide technical support to customers<\/li><\/ol><p><strong>Job Requirements: <\/strong><\/p><ol><li>Candidate should possess a bachelor\u2019s or master\u2019s degree in the field of Electrical or Electronics Engineering, Computer Science or equivalent.<\/li><li>At least 3 years of experience in ASIC\/FPGA\/Embedded system design.<\/li><li>In-depth knowledge and expertise in VHDL, Verilog, System-Verilog, UVM, C and C++<\/li><li>Well versed of ASIC\/Xilinx\/Altera design flow.<\/li><li>Familiar with UNIX\/Linux environment and scripting.<\/li><li>Self-motivated, creative, resourceful, strong analytical and troubleshooting skills.<\/li><li>Should be able to work independently, has a good team spirit, a strong sense of responsibility, a creative problem solver and be easy to get along with others.<\/li><\/ol><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<div class=\"elementor-accordion-item\">\n\t\t\t\t\t<div id=\"elementor-tab-title-1682\" class=\"elementor-tab-title\" data-tab=\"2\" role=\"button\" aria-controls=\"elementor-tab-content-1682\" aria-expanded=\"false\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon elementor-accordion-icon-left\" aria-hidden=\"true\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon-closed\"><i class=\"far fa-plus-square\"><\/i><\/span>\n\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon-opened\"><i class=\"far fa-minus-square\"><\/i><\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t<a class=\"elementor-accordion-title\" tabindex=\"0\">Principal\/ Senior Staff\/Staff\/Design Verification Engineer<\/a>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<div id=\"elementor-tab-content-1682\" class=\"elementor-tab-content elementor-clearfix\" data-tab=\"2\" role=\"region\" aria-labelledby=\"elementor-tab-title-1682\"><p><strong>Job Description:<\/strong><\/p><ul><li>Responsible for IP level and\/or SOC level verification.<\/li><li>Develop verification plan for complex digital IP from design spec, work closely with design engineers to identify important verification scenarios.<\/li><li>Create verification environment\/testbench with Bus Functional Model (BFM) using SystemVerilog, UVM and\/or System C.<\/li><li>Identify and implement functional coverage and SystemVerilog Assertions to catch functional bugs and to boost design quality prior to tape-out.<\/li><li>Develop directed\/use case\/random test cases using SystemVerilog, analyse test results, debug tests and improve verification quality.<\/li><li>Knowing to use Formal verification with SystemVerilog Assertion (SVA) to verify IP block is a plus.<\/li><\/ul><p><strong>Requirements:<\/strong><\/p><ul><li>Bachelor\/Master\u2019s degree in Electrical &amp; Electronics\/Computer Engineering or equivalent.<\/li><li>Familiar with AMBA bus protocol (AXI, CHI, ACE, APB).<\/li><li>Experience with verification methodology such as SystemVerilog, OVM, UVM, SystemC.<\/li><li>Experience with functional coverage\/SVA assertions and test sequence\/case writing.<\/li><li>Experience with the full verification execution cycle.<\/li><li>Experience in developing measurable verification plan.<\/li><li>Experience with function verification for common SoC building blocks and verification IP for NOC\/Interconnect\/Fabric\/PCIE, etc. are added advantages.<\/li><li>Strong problem solver, communicator and team player.<\/li><li>Scripting skills in Perl, Python, TCL, shell, etc.<\/li><\/ul><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<div class=\"elementor-accordion-item\">\n\t\t\t\t\t<div id=\"elementor-tab-title-1683\" class=\"elementor-tab-title\" data-tab=\"3\" role=\"button\" aria-controls=\"elementor-tab-content-1683\" aria-expanded=\"false\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon elementor-accordion-icon-left\" aria-hidden=\"true\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon-closed\"><i class=\"far fa-plus-square\"><\/i><\/span>\n\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon-opened\"><i class=\"far fa-minus-square\"><\/i><\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t<a class=\"elementor-accordion-title\" tabindex=\"0\">Principal\/Senior Staff\/Staff\/Senior IC Layout Engineers<\/a>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<div id=\"elementor-tab-content-1683\" class=\"elementor-tab-content elementor-clearfix\" data-tab=\"3\" role=\"region\" aria-labelledby=\"elementor-tab-title-1683\"><p><strong>Job Description: <\/strong><\/p><ol><li>Work with IC Design engineer to design and layout custom RF, analog and mixed-signal circuits from sub-blocks to top-level integration and verification.<\/li><li>Perform physical design verifications (LVS\/DRC\/ERC).<\/li><li>Collaborate with IC Design engineers to optimize layout implementation for better power, performance, and area.<\/li><li>Responsible for full-chip physical verification sign-off and tape out.<\/li><li>Good understanding of semiconductor and circuit design.<\/li><\/ol><p><strong>Job Requirements: <\/strong><\/p><ol><li>Bachelor degree in Electrical and Electronics Engineering or equivalent.<\/li><li>At least three (5+) or more years of RF, analog \/mixed custom layout design experience.<\/li><li>Experience with schematic-driven layout, floor planning, chip level routing, design rule and physical verification and chip integration.<\/li><li>Good understanding of critical device matching, high voltage layout techniques, advance node Pmos\/ Nmos guarding.<\/li><li>Good knowledge of design manual.<\/li><li>Good Knowledge of CAD tools (Cadence Virtuoso, Mentor Calibre DRC\/LVS\/ERC, Synopsys Hercules, Cadence PVS ).<\/li><li>Must have good analysis and trouble shooting skills.<\/li><li>Should be able to work independently, self-motivated, has a good team spirit, a strong sense of responsibility and urgency, a creative problem solver and hardworking.<\/li><li>Good communication skills in written and verbal English.<\/li><\/ol><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>","protected":false},"excerpt":{"rendered":"<p>Join Our Team We have ongoing opportunities for enthusiastic and motivated individuals who have the experience, skills, and drive to join our team and help propel us forward. Please check the current job opportunities below that are open for application. Please send your Resume to hr@advinno.com. Job Openings Senior AI\/ASIC\/FPGA\/Embedded Design Engineers Job Description: Design [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-6342","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.advinno.com\/sg\/wp-json\/wp\/v2\/pages\/6342","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.advinno.com\/sg\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.advinno.com\/sg\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.advinno.com\/sg\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.advinno.com\/sg\/wp-json\/wp\/v2\/comments?post=6342"}],"version-history":[{"count":74,"href":"https:\/\/www.advinno.com\/sg\/wp-json\/wp\/v2\/pages\/6342\/revisions"}],"predecessor-version":[{"id":6462,"href":"https:\/\/www.advinno.com\/sg\/wp-json\/wp\/v2\/pages\/6342\/revisions\/6462"}],"wp:attachment":[{"href":"https:\/\/www.advinno.com\/sg\/wp-json\/wp\/v2\/media?parent=6342"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}