Services

Structured ASIC Design Services

As semiconductor processes migrate to the deep submicron era, the cost to fabricate standard cell ASIC also skyrocketed. This is primarily due to the rapidly increasing mask costs.

As a result, field programmable gate array (FPGA) has been gaining popularity as an alternative development methodology of ASICs. FPGA-based products uniquely address the economic issues for lower volume applications by being easy to design and program within the shortest possible time. However, FPGAs consume more power, are much lower in performance, and with higher unit costs when compared with standard cell ASICs.

To solve this dilemma, a new breed of gate-array ASIC products, called "Structured ASIC" has emerged. When compared with standard cell-based ASICs, Structured ASICs technology aimed at dramatically reducing the overall fabrication cost and time of customized high performance semiconductor chips, efficiently utilizing standard manufacturing processes.

Advinno Technologies is eASIC Design Services Representative, please contact us for a NRE-Free ASIC Solutions.

Structured ASIC Design Diagram

Back to top